Personally I don’t think we are going to see the road between memory and storage be all that muddled sooner or later. Sure, 3D XPoint is much more responsive than Flash. However Flash isn’t all that spectacular as is. The standard hard drive has access latencies round 4ms on common. Flash can attain nicely bellow µs latency, but for very small arrays. This is costly and mostly seen in Microcontrollers that execute directly from their Flash. "Enterprise grade" flash that optimizes at value/GB can have far larger latency, in the few to tens of µs area. 3D Xpoint is a little bit of a wash. I have seen quoted figures of sub 350ns write latency, however that is probably going for a single cell, not an array. Optane modules from Intel then again have typical latencies around 5-15µs, however that is from a "system" perspective, ie, protocol and controller overhead comes into play, as well as one’s software program surroundings.
DRAM however has entry latencies round 2-15ns at current. The issue with latency is that it results in our processor stalling on account of not getting the info in time. One can prefetch, however branches makes prefetching tougher, since what facet should you fetch? Branch prediction partly solves this situation. However from a efficiency standpoint, we should always fetch each sides. But when we have now more latency, we have to prefetch even earlier, risking extra branches. In other phrases, peak bandwidth required by our processor increases at an exponential price in comparison with latency. A price that's utility dependent as well. Caching might seem just like the trivial resolution to the problem, however the efficiency of cache is proportional to the latency. To a level, cache is a magic bullet that just makes memory latency disappear. But each time an application calls for something that isn’t in cache, then the applying stalls, so long as there's threads to take its place that even have information to work on, you then won’t have a performance deficit aside from thread switching penelties, however in case you don’t have such threads, then the CPU stalls.
One can make sure that extra threads have their data by just making the cache bigger, but cache is quite a bit dearer than DRAM. Ultimately, it all leads to the fact that rising latency will require an arbitrary amount more cache for the same system efficiency. Going from the few ns latency of DRAM to the couple of µs latency of present persistent memory will not be life like as an actual replacement for DRAM, even when it reduces its latency to a 100th it remains to be not impressive as far as memory goes. Though, the use of persistent DIMMs for storage caching or as a "RAM drive" of sorts still has major benefits, but for program execution it is laughable. And i don’t suspect this to change any time soon. However I can see a future the place the principle Memory Wave Program relocates into the CPU. The place the CPU itself has an HBM memory chip or four on it supplying relatively low latency and high bandwidth memory to the CPU, while the exterior buses are used for IO and storage. But this isn’t all that lifelike in more skilled functions, since some workstation purposes truthfully wants 10’s-100’s of GB of actual RAM to get good efficiency.
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